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SPECIFICATION
for
MRD510B
Single Channel F2F Decoder IC
Uniform Industrial Corp.
Taiwan, Factory 1st FL., No.1, Lane 15, Chih Chiang Street, Tu Cheng City, Taipei Hsien, Taiwan, R.O.C. Tel Fax E-mail : 886-2-268-7075 : 886-2-268-6327 : uniform@ms1.hinet.com USA, Office 46750 Fremont Blvd Suite 104 Fremont, CA 94538 USA Tel Fax E-mail : 1-510-438-6799 : 1-510-438-6790 : uicu@aol.com PREPARED BY
APPROVED BY
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CONTENTS
1. DESCRIPTION..................................................................................................... 1 2. FEATURES.......................................................................................................... 1 3. APPLICATIONS .................................................................................................. 1 4. PIN DESCRIPTION ............................................................................................. 2 5. FUNCTION DESCRIPTION................................................................................ 2 6. ABSOLUTE MAXIMUM RATINGS ................................................................... 3 7. RECOMMENDED OPERATING CONDITIONS............................................... 3 8. APPLICATION CIRCUIT .................................................................................... 4 9. TIMING DIAGRAM FOR MRD510B.................................................................. 5 10. OUTLINE DIMENSION ..................................................................................... 6
Uniform Industrial Corp. MRD510B Single Channel F2F Decoder IC
1. DESCRIPTION
The MRD510B is a 1.2um CMOS integrated circuit for purpose of amplification and decoding for F2F magnetic stripe encoding card reader.
2. FEATURES
l l l l l l l Integrated Amplification Circuitry for magnetic head signals. Number of start bits (4/8 bits) to ignore selectable. Both output polarity supported. Adjustable read data output clock pulse width. Single channel support for 75/210 BPI recording density. Magnetic head data input frequency range from 300 bit/sec to 12600 bit/sec. Idle mode controllable by external hardware or micro-processor.
3. APPLICATIONS
l l Magnetic stripe card reader. POS keyboard. PIN Configuration (Top View)
GND SEN1N SEN1P OP1OUT OP2NIN OP2OUT OP3OUT VREFIN VDD NC
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
RES ADJ1 CLS OUT OUTX OCK IBS OSCO OSCI VDD
OUTLINE SOP 20 PIN
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Uniform Industrial Corp. MRD510B Single Channel F2F Decoder IC
4. PIN DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND SEN1N SEN1P OP1OUT OP2NIN OP2OUT OP3OUT VREFIN VDD NC VDD OSCI OSCO IBS OCK OUTX OUT CLS ADJ RES Input from magnetic head Input from magnetic head Amplifier OP1 output Amplifier OP2 - input Amplifier OP2 output Amplifier OP3 output Reference voltage for analog signal processing
RC oscillator input RC oscillator output Select ignore leading bit, "LOW" for 4 bits and "HIGH" for 8 bits Negative read out clock for F2F channel 1 Negative read out data for F2F channel 1 Positive read out data for F2F channel Card Loading Signal output, "LOW" after ignore bits, "HIGH" if no input for around 12.5mS Adjust read out clock pulse width for F2F channel 1 Power on reset, LOW reset the logic circuit and enter idle mode. Approx. 10mS after HIGH level to normal function
5. FUNCTION DESCRIPTION
Data signal inputs read from a magnetic card via a magnetic head are fed into the SEN1P and SEN1N pins, amplified and wave shaped by internal analog circuitry, then converted to logic level F2F data format. Once the F2F signals are detected, the decoding logic ignores the leading 4 or 8 bits (set by IBS pin), via the ignored bits the reference bit length is determined. The succeeding inputs are identified as bit 0 or 1 by the average bit length of preceding two bits, if the data toggles before 70% of the reference bit length then the data is identified as a "1" bit and the next data toggle regarded as the beginning of next data bit. If the data toggles after 70% of the reference bit length then the data is identified as a "0" bit and the current data toggle is as the beginning of next data. After the ignored bits, then pin CLS will be pulled low, the succeeding data bit will be shifted out after the beginning of next data bit. The pin OCK will be pulled low after the next data is detected and a 12uS delay inserted, it will be kept low for 14 to 60uS depending on the external resistor connected to pin ADJ. If the next bit comes before OCK goes high, then OCK1 (OCK2) will be forced to pull high and then begins next cycle, it means that the data signals will be ready before OCK goes low and stay valid till 12uS before next down edge of OCK.
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Uniform Industrial Corp. MRD510B Single Channel F2F Decoder IC
6. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter VDD IBS,OSCI,RES,ADJ1,ADJ2 Conditions Ratings -0.5 to +7.0 -0.5 to VCC +0.5 Unit V V VCC Supply Voltage VIN1 Input Voltage VIN2 Input Voltage
OP2NIN,OP5NIN -0.5 to VCC +0.5 V OP1OUT,OP2OUT,OP3OUT, mA OP4OUT,OP5OUT,OP6OUT, -10 to +10 IO Output Current OSCO2,OUT2,OUT2X,OUT1, OUT1X,OCK1,OCK2 SEN1P ~ SEN1N, V -1.0 to +1.0 VID Differential Input Voltage SEN2P ~SEN2N TOPR Operating Temperature -10 to +70 J TSTG Storage Temperature -50 to +140 J
7. RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Conditions Ratings Unit Min. Typ. Max. 4.5 5 5.5 V VCC -0.5 VCC +0.5 V -0.5 0 0.5 V -1.5 -0.1 3 5 300 2.3 30 3.4 2.5 1.6 4.0 3.0 2.0 80 13000 mA mA mA mV Hz MHz Kohm mA mA mA
VCC Supply Voltage VIH Input High Voltage IBS, RES VIL Input Low Voltage IBS, RES Output High Source OCK1,OUT1,OUT1X, IOH Current at VOH=VCC -0.4 OCK2, OUT2,OUT2X Output High Source IOH CLS Current at VOH=VCC -0.4 OCK1,OUT1,OUT1X, Output Low Sink Current IOL OCK2,OUT2, at VOL=0.4 OUT2X,CLS SEN1P ~ SEN1N VIN Differential Input Voltage SEN2P ~ SEN2N SEN1P ~ SEN1N FIN Input Frequency SEN2P ~ SEN2N FOSC Oscillation Frequency External resistor between ROSC OSCI & OSCO IOPR Signal input at 12.6K bps ISBY No signal input IDLE Reset = Vss
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Uniform Industrial Corp. MRD510B Single Channel F2F Decoder IC
8. APPLICATION CIRCUIT
5V 1M 0.1u
5V Mag. head 3.3K 3300p 47p OP1OUT OP2NIN OP2OUT OP3OUT SEN1N SEN1P RES ADJ 1K~3M IBS OSCO Rocs=30K(5V) OSCI OCK OUT OUTX CLS VREFIN 2.2u 5V VDD 5V 10K CLS 5V
GND
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October, 1997
Uniform Industrial Corp. MRD510B Single Channel F2F Decoder IC
9. TIMING DIAGRAM FOR MRD510B
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October, 1997
Uniform Industrial Corp. MRD510B Single Channel F2F Decoder IC
10. OUTLINE DIMENSION
Symbol A A1 b c D E
Dimensions in inch 0.106 Max. 0.004 Min. 0.016 +0.004 -0.002 0.010 +0.004 -0.002 0.504 typ (0.524 Max) 0.295 +/-0.005 0.050 +/-0.006 0.374 Nor. 0.406 +/-0.010 0.032 +/-0.008 0.055 +/-0.008 0.042 Max. 0.006 Max. 0X~ 8X
Dimensions in mm 2.692 Max. 0.102 Min. 0.406 +0.102 -0.051 0.254 +0.10 -0.05 12.802 typ (13.310 Max) 7.493 +/-0.13 1.270 +/-0.152 9.50 Nor. 10.312 +/-0.254 0.813 +/-0.203 1.397 +/-0.203 1.067 Max. 0.152 Max. 0X~ 8X
e
e1 HE L LE S y K
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October, 1997

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